The present invention relates to the field of equalization in high-speed receiving units, particularly to a continuous-time linear equalization. Furthermore, the present invention relates to a structure and method a continuous-time linear equalizer suitable for the implementation in integrated circuitry, particularly in Complementary Metal-Oxide Semiconductor (CMOS) technology.
Data transceiving systems for high-speed communication are subject to signal attenuation and distortion of the transmitted signal. Various measures are applied to reconstruct the transmitted data from the received analog signal. In receiving units, a number of equalizers are commonly provided to compensate for losses and signal distortion substantially caused by propagating the data signal via the transmission channel.
Continuous time linear equalizers (CTLE) are used in the receiving units in order to equalize the transmission channel attenuation up to a peaking frequency by means of a high-pass transfer function, which counterbalances the low-pass characteristic of the transmission channel.
The CTLE typically operates on both data- and clock-paths. Therefore, the signal integrity at both the maximum amplitude (a.k.a. eye center) and at the zero crossings of the received signal should be equalized.